Technical: VHDL Codes

1) Module Name: Basic_gates - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Basic_gates is

Port ( a,b : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (4 downto 0));

end Basic_gates;

architecture Behavioral of Basic_gates is

begin

y(0)<=a and b;

y(1)<=a or b;

y(2)<=not a;

y(3)<=a xor b;

y(4)<=a xnor b;

end Behavioral;

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2) Module Name: universal gate ug_b - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity ug_b is

Port ( a,b : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (1 downto 0));

end ug_b;

architecture u_g of ug_b is

begin

process(a,b)

begin

if a='0' and b='0' then

y(0)<='1';

else

y(0)<='0';

end if;

if a='1' and b='1' then

y(1)<='0';

else

y(1)<='1';

end if;

end process;

end u_g;

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3) Module Name: Universal_gates1 ( Dataflow)

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Universal_gates1 is

Port ( a,b : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (1 downto 0));

end Universal_gates1;

architecture u_g of Universal_gates1 is

begin

y(0)<= a nand b;

y(1)<=a nor b;

end u_g;

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4) Module Name: Basics_gates And,Or Xor - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity and_or_xor_xnor is

Port ( a,b : in STD_LOGIC;

w : out STD_LOGIC;

x : out STD_LOGIC;

y : out STD_LOGIC;

z : out STD_LOGIC);

end and_or_xor_xnor;

architecture Behavioral of and_or_xor_xnor is

begin

process(a,b)

begin

if a='1' and b='1' then

w<='1';

else

w<='0';

end if;

if a<='0' and b='0' then

x<='0';

else

x<='1';

end if;

if a<='1' and b<='1' then

y<='0';

elsif a<='0' and b<='0' then

y<='0';

else y<='1';

end if;

if a<='0' and b<='0' then

z<='1';

elsif a<='0' and b<='0' then

z<='1';

else z<='0';

end if;

end process;

end Behavioral;

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5) Module Name: Driver - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Driver is

Port ( a : in STD_LOGIC;

y : out STD_LOGIC);

end Driver;

architecture Drive of Driver is

begin

y<=a;

end Drive;

-------------------------------------------------------------------

6) Module Name: Half Adder HA - Behavioral

-------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity HA is

Port ( A_h : in STD_LOGIC;

B_h : in STD_LOGIC;

S_h : out STD_LOGIC;

C_h : out STD_LOGIC);

end HA;

architecture Half_adder of HA is

begin

S_h<=A_h xor B_h;

C_h<=A_h and B_h;

end Half_adder;

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7) Module Name: Full_adder-using_Half_adder - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity full_adder is

Port ( A_f : in STD_LOGIC;

B_f : in STD_LOGIC;

C_in : in STD_LOGIC;

S_f : out STD_LOGIC;

C_f : out STD_LOGIC);

end full_adder;

architecture full of full_adder is

component HA

port (A_h : in STD_LOGIC;

B_h : in STD_LOGIC;

S_h : out STD_LOGIC;

C_h : out STD_LOGIC);

end component;

signal S1,C1,C2:STD_LOGIC;

begin

HA1 : HA port map (A_f,B_F,S1,C1);

HA2 : HA port map (S1,C_in,S_f,C2);

C_f<= c1 or c2;

end full;

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8) Module Name: 3:8 Decoder - Behavioral (concurrent)

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder38 is

Port ( a : in STD_LOGIC_VECTOR (2 downto 0);

y : out STD_LOGIC_VECTOR (7 downto 0);

g : in STD_LOGIC_VECTOR (2 downto 0));

end decoder38;

architecture Concurrent of decoder38 is

begin

with a&g select

y<="11111110" when "000100",

"11111101" when "001100",

"11111011" when "010100",

"11110111" when "011100",

"11101111" when "100100",

"11011111" when "101100",

"10111111" when "110100",

"01111111" when "111100",

"11111111" when others;

end Concurrent;

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9) Module Name: 3:8 Decoder - Behavioral ( Sequential)

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity decoder38 is

Port ( y : out STD_LOGIC_VECTOR (7 downto 0);

a : in STD_LOGIC_VECTOR (2 downto 0);

g : in STD_LOGIC_VECTOR (2 downto 0));

end decoder38;

architecture sequ of decoder38 is

begin

process(a,g)

begin

if g="100" then

case a is

when "000" => y<="11111110";

when "001" => y<="11111101";

when "010" => y<="11111011";

when "011" => y<="11110111";

when "100" => y<="11101111";

when "101" => y<="11011111";

when "110" => y<="10111111";

when others =>y<="01111111";

end case;

else

y<="11111111";

end if;

end process;

end sequ;

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10) Module Name: 4:1mux - Behavioral (Dataflow)

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux is

Port ( s : in STD_LOGIC_VECTOR (1 downto 0);

a : in STD_LOGIC_VECTOR (3 downto 0);

en : in STD_LOGIC;

y : out STD_LOGIC);

end mux;

architecture Behavioral of mux is

signal p:STD_LOGIC_VECTOR(3 downto 0);

begin

p(0)<= (not s(1)) and (not s(0)) and (not en) and a(0);

p(1)<= (not s(1)) and s(0) and (not en) and a(1);

p(2)<= s(1) and (not s(0)) and (not en) and a(2);

p(3)<= s(1) and s(0) and (not en) and a(3);

y<=p(0) or p(1) or p(2) or p(3);

end Behavioral;

------------------------------------------------------------------------------

11-a) Module Name: 8:1 mux - Behavioral (concurrent)

------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_81_conc is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

en : in STD_LOGIC;

s : in STD_LOGIC_VECTOR (2 downto 0);

y : out STD_LOGIC;

yb : out STD_LOGIC);

end mux_81_conc;

architecture concurrent of mux_81_conc is

signal x,temp:std_logic;

begin

with s select

temp<=a(0) when "000",

a(1) when "001",

a(2) when "010",

a(3) when "011",

a(4) when "100",

a(5) when "101",

a(6) when "110",

a(7) when others;

x<=temp when en='0' else '0';

y<=x;

yb<= not x;

end concurrent;

---------------------------------------------------------------------

11-b) Module Name: 8:1 mux - Behavioral (Sequential)

----------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_81 is

Port ( a : in STD_LOGIC_VECTOR (7 downto 0);

s : in STD_LOGIC_VECTOR (2 downto 0);

en : in STD_LOGIC;

y,yb : out STD_LOGIC);

end mux_81;

architecture Sequential of mux_81 is

signal x: STD_LOGIC;

begin

process(a,s,en)

begin

if en='1' then x<='0';

else

case s is

when "000" => x<=a(0);

when "001" => x<=a(1);

when "010" => x<=a(2);

when "011" => x<=a(3);

when "100" => x<=a(4);

when "101" => x<=a(5);

when "110" => x<=a(6);

when others => x<=a(7);

end case;

end if;

end process;

y<=x;

yb<=not x;

end Sequential;

---------------------------------------------------------------------------

12) Module Name: 16_1 Mux_using-4_1 mux

---------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux_16_1 is

Port ( d : in STD_LOGIC_VECTOR (15 downto 0);

sel : in STD_LOGIC_VECTOR (3 downto 0);

x : out STD_LOGIC;

e : in STD_LOGIC);

end mux_16_1;

architecture Behavioral of mux_16_1 is

component mux_41

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

s : in STD_LOGIC_VECTOR (1 downto 0);

y : out STD_LOGIC;

en : in STD_LOGIC);

end component;

signal z:std_logic_Vector(3 downto 0);

begin

mux1:mux_41 port map (d(3 downto 0),sel(1 downto 0),z(0),e);

mux2:mux_41 port map (d(7 downto 4),sel(1 downto 0),z(1),e);

mux3:mux_41 port map (d(11 downto 8),sel(1 downto 0),z(2),e);

mux4:mux_41 port map (d(15 downto 12),sel(1 downto 0),z(3),e);

mux5:mux_41 port map (z,sel(3 downto 2),x,e);

end Behavioral;

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13) Module Name: 16_1 MUX_using-8_1 MUX_&_2_1 MUX - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mux16 is

Port ( c : in STD_LOGIC_VECTOR (15 downto 0);

se: in STD_LOGIC_VECTOR (3 downto 0);

e2 : in STD_LOGIC;

z : out STD_LOGIC);

end mux16;

architecture Behavioral of mux16 is

component mux_81

Port ( b : in STD_LOGIC_VECTOR (7 downto 0);

sel : in STD_LOGIC_VECTOR (2 downto 0);

e1 : in STD_LOGIC;

x1 : out STD_LOGIC);

end component;

component mux_21

Port ( a : in STD_LOGIC_VECTOR (1 downto 0);

s : in STD_LOGIC;

e : in STD_LOGIC;

x : out STD_LOGIC);

end component;

signal R :std_logic_vector (1 downto 0);

begin

mux1:mux_81 port map (c(7 downto 0),se(2 downto 0),e2,r(0));

mux2:mux_81 port map (c(15 downto 8), se(2 downto 0),e2,r(1));

mux3:mux_21 port map (r,se(3),e2,z);

end Behavioral;

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14) Module Name: Parity 9_bit - Behavioral

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library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bit_9 is

Port ( i : in STD_LOGIC_VECTOR (8 downto 0);

even,odd : out STD_LOGIC);

end bit_9;

architecture Behavioral of bit_9 is

component bit_3

Port ( a,b,c : in STD_LOGIC;

y : out STD_LOGIC);

end component;

signal t:std_logic_vector(2 downto 0);

begin

t1:bit_3 port map (i(0),i(1),i(2),t(0));

t2:bit_3 port map (i(3),i(4),i(5),t(1));

t3:bit_3 port map (i(6),i(7),i(8),t(2));

t4:bit_3 port map (t(0),t(1),(not t(2)),even);

t5:bit_3 port map (t(0),t(1),t(2),odd);

end Behavioral;

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15) Module Name: Comparator - Behavioral

------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity comparator is

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);

l,e,g : in STD_LOGIC;

l1,e1,g1 : out STD_LOGIC);

end comparator;

architecture Behavioral of comparator is

begin

process(a,b,l,e,g)

begin

if a>b then

l1<='0'; e1<='0'; g1<='1';

elsif a<b then

l1<='1'; e1<='0'; g1<='0';

else

if e='1' then

l1<='0'; e1<='1'; g1<='0';

elsif l=g then

l1<=not l; e1<='0'; g1<=not g;

else

l1<=l; e1<='0'; g1<=g;

end if;

end process;

end Behavioral;

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16) Module Name: Cascade-of-Comparator_IC7485 - Behavioral

--------------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity bitcomp8 is

Port ( C : in STD_LOGIC_VECTOR (7 downto 0);

D : in STD_LOGIC_VECTOR (7 downto 0);

gr,ls,eq : in STD_LOGIC;

gr1,ls1,eq1 : out STD_LOGIC);

end bitcomp8;

architecture Behavioral of bitcomp8 is

component comparator

Port ( a,b : in STD_LOGIC_VECTOR (3 downto 0);

l,e,g : in STD_LOGIC;

l1,e1,g1 : out STD_LOGIC);

end component;

signal t_l,t_e,t_g: std_logic;

begin

IC1:comparator port map (c(3 downto 0),d(3 downto 0),'0','1','0',t_l,t_e,t_g);

IC2:comparator port map (c(7 downto 4),d(7 downto 4),t_l,t_e,t_g,ls1,eq1,gr1);

end Behavioral;

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17) Module Name: D-Flipflop - Behavioral

------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity DFlipflop is

Port ( D : in STD_LOGIC;

CLK,reset : in STD_LOGIC;

Q,Q_b : out STD_LOGIC);

end DFlipflop;

architecture Behavioral of DFlipflop is

signal temp:std_logic;

begin

process(clk,reset)

begin

if reset ='1' then

temp<='0';

elsif clk'event and clk='1' then

temp<=D;

end if;

end process;

Q<=temp;

Q_b<=not temp;

end Behavioral;

-------------------------------------------------------------

18) Module Name: T-FLIPFLOP - Behavioral

-------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity T-FLIPFLOP is

Port ( T,clk,reset : in STD_LOGIC;

Q_b : out STD_LOGIC;

Q : out STD_LOGIC);

end TFLIPFLOP;

architecture Behavioral of T-FLIPFLOP is

signal temp:STD_LOGIC;

begin

process (clk,reset)

begin

if reset='1' then

temp<='0';

elsif clk'event and clk='1' then

if T='1' then

temp<=not temp;

else

temp<=temp;

end if;

end process;

q<=temp;

q_b<=not temp;

end Behavioral;

------------------------------------------------------------------

19) Module Name: JK Flip Flop jkffs - Behavioral

------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity JKFlipflop is

Port ( J : in STD_LOGIC;

K : in STD_LOGIC;

CLK : in STD_LOGIC;

RESET : in STD_LOGIC;

Q : out STD_LOGIC;

Q_b : out STD_LOGIC);

end JKFlipflop;

architecture Behavioral of JKFlipflop is

signal t:std_logic ;

begin

process(CLK,RESET)

begin

if reset='1' then

t<='0';

elsif clk'event and CLK='1' then

if J='0' and K='0' then

t<=t;

elsif J='0' and K='1' then

t<='0';

elsif J='1' and K='0' then

t<='1';

else

t<=not t;

end if;

end process;Q<=t;

Q_b<=not t;

end Behavioral;

------------------------------------------------------------

20) Module Name: Mealy Circuit - Behavioral

------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity mealy is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

y : out STD_LOGIC;

x : in STD_LOGIC);

end mealy;

architecture Behavioral of mealy is

type sequence is (a,b,c,d);

signal P_S,N_S:sequence;

begin

process(clk,reset)

begin

if (reset='1') then

P_S<=a;

elsif(clk'event and clk='1') then

P_S<=N_S;

end if;

end process;

process(x,P_S)

begin

case P_S is

when a=>

if (x='0') then

y<='0';

N_S<=a;

else

y<='0';

N_S<=b;

end if;

when b=>

if (x='0') then

y<='0';

N_S<=c;

else

y<='0';

N_S<=b;

end if;

when c=>

if (x='0') then

y<='0';

N_S<=a;

else

y<='0';

N_S<=d;

end if;

when d=>

if (x='0') then

y<='1';

N_S<=c;

else

y<='0';

N_S<=b;

end if;

end case;

end process;

end Behavioral;

----------------------------------------------------------

21) Module Name: Moore circuit - Behavioral

-----------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity moore is

Port ( x : in STD_LOGIC;

clk,reset : in STD_LOGIC;

y : out STD_LOGIC);

end moore;

architecture Behavioral of moore is

type sequence is (a,b,c,d);

signal P_S,N_S:sequence;

begin

process(clk,reset)

begin

if (reset='1') then

P_S<=a;

elsif(clk'event and clk='1') then

P_S<=N_S;

end if;

end process;

process(x,P_S)

begin

case P_S is

when a=>

y<='0';

if (x='0') then

N_S<=a;

else

N_S<=b;

end if;

when b=>

y<='0';

if (x='0') then

N_S<=a;

else

N_S<=c;

end if;

when c=>

y<='0';

if (x='0') then

N_S<=a;

else

N_S<=d;

end if;

when d=>

y<='1';

if (x='0') then

N_S<=a;

else

N_S<=d;

end if;

end case;

end process;

end Behavioral;

-----------------------------------------------------------

22) Module Name: Up_counter - Behavioral

-----------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Up_counter is

Port ( clk,reset : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR (3 downto 0));

end Up_counter;

architecture Behavioral of Up_counter is

signal t:STD_LOGIC_VECTOR (3 downto 0);

begin

process (clk,reset)

begin

if reset='1' then

t<="0000";

elsif clk'event and clk='1' then

t<=t+1;

end if;

end process;

q<=t;

end Behavioral;

---------------------------------------------------------------

23) Module Name: Down_counter - Behavioral

---------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Down_counter is

Port ( clk,reset : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR (3 downto 0));

end Down_counter;

architecture Behavioral of Down_counter is

signal t:STD_LOGIC_VECTOR (3 downto 0);

begin

process (clk,reset)

begin

if reset='1' then

t<="1111";

elsif clk'event and clk='1' then

t<=t-1;

end if;

end process;

q<=t;

end Behavioral;

--------------------------------------------------------------------

24) Module Name: Up down_counter - Behavioral

--------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity updown is

Port ( clk : in STD_LOGIC;

reset : in STD_LOGIC;

mode : in STD_LOGIC;

q : out STD_LOGIC_VECTOR (3 downto 0));

end updown;

architecture Behavioral of updown is

signal t: std_logic_vector (3 downto 0);

begin

process(clk,reset)

begin

if (reset='1') then

t<="0000";

elsif (clk'event and clk='1') then

if (mode='0')then

t<=t+1;

else

t<=t-1;

end if;

end process;

q<=t;

end Behavioral;

----------------------------------------------------------------

25) Module Name: 4 bit counter4bit - Behavioral

----------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity counter4bit is

Port ( Q : out STD_LOGIC_VECTOR (3 downto 0);

RSET,clk : in STD_LOGIC);

end counter4bit;

architecture Behavioral of counter4bit is

component TFF is

Port ( T : in STD_LOGIC;

reset : in STD_LOGIC;

Q1 : out STD_LOGIC;

clk1 : in STD_LOGIC);

end component;

signal tem: std_logic_vector(3 downto 0);

begin

T0:TFF port map ('1',RSET,tem(0),clk);

T1:TFF port map ('1',RSET,tem(1),tem(0));

T2:TFF port map ('1',RSET,tem(2),tem(1));

T3:TFF port map ('1',RSET,tem(3),tem(2));

Q<=tem;

end Behavioral;

-------------------------------------------------------

26) Module Name: IC74163 - Behavioral

-------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity IC74163 is

Port ( A,B,C,D : in STD_LOGIC;

clr,clk,Enp,Ent,load : in STD_LOGIC;

QA,QB,QC,QD,rco : out STD_LOGIC);

end IC74163;

architecture Behavioral of IC74163 is

signal t:std_logic_vector(3 downto 0);

begin

process(A,B,C,D,clr,clk,Enp,Ent,load)

begin

rco<='0';

if (clr='0') then

t<="0000";

elsif (load='0' and clk'event and clk='1') then

t(0)<=A;

t(1)<=B;

t(2)<=C;

t(3)<=D;

elsif (load='1' and Enp='1' and Ent='1' and clk='1' and clk'event) then

t<=t+1;

else

t<=t;

end if;

if (t="1110") then

rco<='1';

end if;

end process;

QA<=t(0);

QB<=t(1);

QC<=t(2);

QD<=t(3);

end Behavioral;

------------------------------------------------------------

27) Module Name: IC_74169 - Behavioral

------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity IC_74169 is

Port ( UD,clk,Enp,Ent,load : in STD_LOGIC;

A,B,C,D : in STD_LOGIC;

QA,QB,QC,QD : out STD_LOGIC;

Rco : out STD_LOGIC);

end IC_74169;

architecture Behavioral of IC_74169 is

signal t:std_logic_vector(3 downto 0);

begin

process(A,B,C,D,clk,Enp,Ent,load)

begin

rco<='1';

if (load='0' and clk'event and clk='1') then

t(0)<=A;

t(1)<=B;

t(2)<=C;

t(3)<=D;

elsif (load='1' and Enp='0' and Ent='0' and clk='1' and clk'event) then

if(UD='1') then

t<=t+1;

else

t<=t-1;

end if;

else

t<=t;

end if;

if (t="0000") then

rco<='0';

end if;

end process;

QA<=t(0);

QB<=t(1);

QC<=t(2);

QD<=t(3);

end Behavioral;

--------------------------------------------

28) Module Name: IC 74194

---------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity univeral_reg is

Port ( a : in STD_LOGIC_VECTOR (3 downto 0);

clr : in STD_LOGIC;

clk,rin,lin : in STD_LOGIC;

s:in std_logic_vector(1 downto 0);

q : out STD_LOGIC_VECTOR (3 downto 0));

end univeral_reg;

architecture Behavioral of univeral_reg is

signal t:STD_LOGIC_VECTOR (3 downto 0);

begin

process(a,clr,rin,lin,s,clk)

begin

if (clr='0') then

t<="0000";--Asynchronous Clear

elsif(clk'event and clk='1') then

case s is

when "00" => t<=t;--Hold

when "01" => t<=rin & t(3 downto 1);--Right shift

when "10" => t<=t(2 downto 0) & lin;--Left shift

when others=> t<=a;--Loading condition

end case;

end if;

end process;

q<=t;

end Behavioral;

-------------------------------------------------------------

29) Module Name: TristateBuffer - Behavioral

--------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity TriBuffer is

Port ( A : in STD_LOGIC_VECTOR (7 downto 0);

En : in STD_LOGIC;

y : out STD_LOGIC_VECTOR (7 downto 0));

end TriBuffer;

architecture tribuff of TriBuffer is

begin

process(A,En)

begin

if En='1' then

y<=A;

else

y<="ZZZZZZZZ";

end if;

end process;

end tribuff;

----------------------------------------------------------------------------------

30) Module Name: Serial in Serial out SISO_shift - Behavioral

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity SISO_shift is

Port ( din,clk,reset : in STD_LOGIC;

q : out STD_LOGIC);

end SISO_shift;

architecture Behavioral of SISO_shift is

signal t:std_logic_vector(7 downto 0);

begin

process(clk,Din,reset)

begin

if(reset='1') then

t<="00000000";

elsif(clk'event and clk='1')then

t<=t(6 downto 0)&din;

end if;

end process;

q<=t(7);

end Behavioral;

----------------------------------------------------------------------------------

31) Module Name: Serial in Parallel out Shift register SIPO 8 bit

----------------------------------------------------------------------------------

library IEEE;

use IEEE.STD_LOGIC_1164.ALL;

use IEEE.STD_LOGIC_ARITH.ALL;

use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity Shiftregister is

Port ( Din : in STD_LOGIC;

reset : in STD_LOGIC;

clk : in STD_LOGIC;

Q : out STD_LOGIC_VECTOR (7 downto 0));

end Shiftregister;

architecture Behavioral of Shiftregister is

signal t:std_logic_vector(7 downto 0);

begin

process(clk,Din,reset)

begin

if(reset='1') then

t<="00000000";

elsif(clk'event and clk='1') then

t(0)<=Din;

t(1)<=t(0);

t(2)<=t(1);

t(3)<=t(2);

t(4)<=t(3);

t(5)<=t(4);

t(6)<=t(5);

t(7)<=t(6);

end if;

end process;

Q<=t;

end Behavioral;

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